Processor Design Fall 2021

This course offers a more advanced treatment of digital design in the context of microprocessors and accelerators. With a special emphasis on:

Design methodology and practice
Pipelined microprocessor/accelerator architecture implementation and evaluation

Projects related to safety-critical and real-time embedded systems are particularly encouraged.

Previous years: Fall 2020 Fall 2019

Lab Sessions

These labs are initially thought as a continuation of PA-MIRI ones. Should you have not taken PA-MIRI, please contact your lab professor.

Name	Date	Deliverable Due Date	Docs
1.Infrastructure setup and test. Baseline microprocessor selection.	17/9 24/9 (NO LAB) 01/10	08/10	[PD_lab_intro2021_09_14.pdf] [PD_2019_2020_projects.pdf] [lab1.pdf]
2.Module definition and specification. Workplan.	08/10 15/10	22/10	[lab2.pdf]
3. Module implementation and verification in isolation	22/10 29/10 05/11 12/11	12/11	[lab3.pdf]
4. Module Review	Week of 16-20/11		Interview
5. Integration with a pipelined CPU	19/11 26/11 03/12 10/12	10/12
6. Project review	Between 14-23/12		Interview
7. Extension of original module with optional features	17/12 07/01 14/01 21/01	21/01

Each group will choose an advanced feature to extend their baseline processor. Features related to the additions of safety-critical real-time features in existing open-source RISC-V cores are particularly encouraged, as well as releasing the implementations as open source. For example projects, you can take a look at the award winning projects of the 2019 edition.

Bibliography and Useful Links

Weste, N. H., & Harris, D. “CMOS VLSI Design : A Circuits and Systems Perspective”. 4th Edition, 2010.
Kahng AB, Lienig J, Markov IL, Hu J. “VLSI Physical Design: from Graph Partitioning to Timing Closure”. Springer Science & Business Media; 2011 Jan 27.
Mead, C., & Conway, L. (1980). Introduction to VLSI systems (Vol. 1080). Reading, MA: Addison-Wesley.
RISC-V Cores: https://riscv.org/exchange/cores-socs/
OpenPower Cores: https://openpowerfoundation.org/cores-and-more/
OpenCores: https://opencores.org/
Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/
Qflow 1.3: An Open-Source Digital Synthesis Flow: http://opencircuitdesign.com/qflow/

We would like to thank AMD Xilinx for the donation of 3 FPGA Kits for the purporse of this course (PYNQ Z1, 2 x Kria KV260) as well as educational licenses.